1. Field of the Invention
This invention relates to power distribution system design, and in particular to managing disturbances otherwise caused by time varying current demands in an integrated circuit.
2. Description of the Related Art
As high performance integrated circuits demand larger currents at higher frequencies with lower power supply voltages, power system design becomes increasingly challenging. For example, next generation microprocessors will demand peak currents in excess of 100 A and reach operating frequencies of 1 GHz with power supply voltages below 2 V. At such current levels, surge currents and associated excitations of power distribution system resonances can result in significant power supply voltage excursions. Accordingly, reductions in the AC impedance of a power distribution system, particularly inductive components thereof, are desired.
A variety of techniques are available to improve the AC impedance characteristics of a power distribution system. One such technique involves the appropriate placement of decoupling structures/devices, e.g., capacitors, throughout the power distribution system. Others include chip layout with respect to power distribution, use of low inductance packaging technologies such as Controlled Collapse Chip Connection (C4) and Ball Grid Array (BGA) for delivery of supply voltages (V.sub.DD and V.sub.SS), BGA package design and layers, card layout and use of discrete capacitance placed thereon, connector selection and V.sub.DD /V.sub.SS allocations, regulator choice, and lastly the motherboard layout.
In a typical computer system configuration, inductances are associated with the vias, traces, connectors, etc. of an integrated circuit carrier (or "package"), of a daughterboard card, and of a motherboard. At low frequencies (i.e., below approximately 100 KHz), impedance of the power supply loop circuit can be made arbitrarily low through the utilization of feedback voltage sensing at the power supply. At very high frequencies, the impedance of the power supply loop circuit can be lowered with the use of on-die capacitance to approximately (1/.omega.C) where .omega. is the angular frequency (such that .omega.=2.pi.f) and C is the capacitance associated with the power supply loop circuit including the on-die capacitance. Unfortunately, in the mid-frequencies (e.g., from approximately 1 MHz to 100 MHz), the AC impedance of the power supply loop circuit is likely to exhibit resonances.
While the impedance at both high- and mid-frequencies can be managed through the use of decoupling capacitors placed strategically in the power supply loop circuit, two significant challenges exist. First, spatial limitations of an integrated circuit chip can limit the amount of capacitance provided on-die. Typically, only the portions of the die that are free from device structures will be available for fabrication of on-die capacitors. High-frequency, high-current integrated circuits such as advanced microprocessors may require hundreds of nF of on-die capacitance. Even worse, larger capacitances, e.g., .mu.f, will be required to manage mid-frequency resonances. Using conventional gate oxide dielectric techniques and typical gate oxide thicknesses, capacitance on the order of 10 nF per mm.sup.2 can be achieved. Therefore, achieving hundreds to thousands of nF of on-die capacitance requires significant die footprint (e.g., tens to hundreds of mm.sup.2). Such die footprint can adversely affect die size and yield.
Many off-chip decoupling capacitor configurations have been developed. For example, U.S. Pat. No. 4,754,366 to Hernandez discloses flat decoupling capacitors adapted for mounting directly under a Pin Grid Array (PGA) package, directly under a surface-mounted Plastic Leaded Chip Carrier (PLCC), and over a surface-mounted leadless chip carrier. U.S. Pat. No. 4,636,918 to Jodoin and U.S. Pat. No. 5,034,850 to Hernandez et al. disclose other discrete off-chip decoupling capacitor configurations. Unfortunately, the inductive impedance of intervening portions of the power supply loop circuit (e.g., of chip and package -level interconnect features such as vias, traces, bonding pads, wires and wire bonds, Tape Automated Bonded (TAB) traces and bonds, solder bumps including Controlled Collapse Chip Connection (C4) bumps, etc.) typically limits the efficacy of off-chip decoupling capacitors.
In part for this reason, decoupling capacitors have also been provided integral with an integrated circuit package. For example, U.S. Pat. No. 5,258,575 to Beppu et al. discloses a plurality of small discrete decoupling capacitors connected to integral power and ground planes of an integrated circuit package. U.S. Pat. No. 5,475,565 to Bhattacharyya et al. discloses a decoupling capacitor configuration wherein the decoupling capacitor is mounted to and electrically connected to a lid of an electronic package. U.S. Pat. No. 5,049,979 to Hashemi et al. discloses a close attach capacitor attached above the top of a TAB chip wherein short bonded wires or TAB leads interconnect the capacitor electrodes with power and ground pads on the chip.
Unfortunately, even in such configurations, the series inductance from the switching circuits of the integrated circuit to the decoupling capacitance limits the efficacy of the decoupling capacitance. Accordingly, decoupling capacitor configurations are desired which allow placement of large decoupling capacitance on-die with extremely low intervening inductance.